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Preliminary
RT9591
Smart Photoflash Capacitor Charger with IGBT Driver
General Description
The RT9591 is a highly integrated photoflash charging solution in digital and film cameras. It is targeted for applications that use either two AA batteries or a single lithium-ion battery. The RT9591 integrates a constant current controller for charging high voltage photoflash capacitor quickly and efficiently, an IGBT driver for igniting flash tube, and a voltage detector. Only a few external components are used to reduce PCB space and cost. RT9591 is available in VQFN-16L 3x3 package.
Features
1.8V to 6.5V Battery Input Voltage Range Charges Any Size Photoflash Capacitor Adjustable Input Current Uses Standard Transformers Adjustable Output Voltage Charge Complete Indicator Built-in IGBT Driver for IGBT Application Built-in Voltage Detector 16-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free
Applications Ordering Information
RT9591 Package Type QV : VQFN-16L 3x3 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Digital Still Camera Film Camera Flash Unit Camera Phone Flash
Pin Configurations
(TOP VIEW)
GNDDRV 12 11 10 9 DRVOUT VDRV IMCD VDOUT FBVD
Note : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.
FB PGND EXT GND 1 2 3 4 VDD CS DRVIN CHARGE STAT VBAT
Richtek Pb-free and Green products are :
16 15 14 13 GND 17 5678
Marking Information
For marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail.
VQFN-16L 3x3
Patent Pending DS9591-07 August 2007 www.richtek.com 1
RT9591
Typical Application Circuit
Delta 86A-3145 T1 1 : 15 CIN R6 1.5M 10uF SW AO3400 Q1
Preliminary
VBAT 1.8V to 6.5V
VOUT GSD2004S
+
COUT 100uF/ 300V
Flash-Tube
R1 150k 0805
10
VBAT
IMCD
EXT
R7 1M VDD 3.3V 1uF
16 8 5
3
FBVD VDD
5V
R8 100k
6
RT9591
VDOUT
7
Strobe DRVIN 14 11 VDRV
12 13 1
R2 150k 0805
DRVOUT GNDDRV
GND
9
CS
STAT CHARGE 2 PGND
0.1uF
FB
R4 1M R5 2M
15 4
R3 1k
Figure 1. Photoflash Capacitor Charger Application
VBAT 1.8V to 6.5V
ASATECH ST-532553A T1 1 : 14 CIN 10uF SW AO3400 Q1
VOUT GSD2004S
+
COUT 47uF/ 300V
Flash-Tube
R1 150k 0805
10
16
3
VBAT
EXT
8
FBVD VDD
5V
14 12 13 1
VDD 3.3V 1uF
5
R8 100k
6
RT9591
7
DRVIN 11 VDRV DRVOUT GNDDRV
Strobe 0.1uF
R2 150k 0805
VDOUT
GND
9
CS
STAT CHARGE 2 PGND
IMCD
FB
15 4
R4 560k
R3 1k
Figure 2. Photoflash Capacitor Charger Application for Low Charging Current
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Preliminary
RT9591
VOUT
VBAT 1.8V to 6.5V R5 1.5M
Delta 86A-3145B T1 1 : 15 CIN 10uF 1 14
GSD2004S
+
SW AO3400 Q1
1
COUT 100uF/ 300V
Flash-Tube
R1 19k
VBAT
FBVD VDD
EXT
8 5
IMCD
R6 1M VDD 3.3V
16
3
10
5V
14
1uF
R7 100k
6
RT9591
7
DRVIN 11 VDRV DRVOUT
12
Strobe 0.1uF
VDOUT
GND
9
CS
STAT CHARGE 2 PGND
GNDDRV FB
13 1
R3 1M R4 2M
15 4
R2 1k
Figure 3. Photoflash Capacitor Charger Application with Center-Tap Transformer
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RT9591
Function Block Diagram
VBAT
Preliminary
Charging Block VDD Constant Peak Current Control 1M One Shot Charging Block Enable Q S CHARGE GND FBVD 1.0V Reference DRVIN IGBT Driver VDRV DRVOUT GNDDRV One Shot Voltage Detector HV Detector FB VDOUT Latch R S Q Driver EXT PGND
VDD
CS
+36mV
3.6
IMCD
Chip Enable
Latch R
Functional Pin Description
Pin No. 1 2 3 4 5 6 Pin Name FB PGND EXT GND VDD Feedback Voltage Pin. Power Ground. Output Pin for driving external NMOS on Flyback topology. Ground. Power Input Pin of RT9591. Charge Enable Pin, the charge function is executed when CHARGE pin is set from CHARGE Low to High. And the RT9591 gets into Shutdown mode when CHARGE pin is set to Low. 7 8 9 10 11 12 13 14 15 16 STAT FBVD VDOUT IMCD VDRV Charge Status Output. Open Drain output. When target output voltage is reached, N-MOSFET turns off. This pin needs a pull up resistor. Voltage Detector Feedback Pin. Voltage Detector Output Pin, Open Drain output. Minimum Current Detection Pin. IGBT Driver Power Pin. Pin Function
DRVOUT IGBT Driver Output Pin. GNDDRV IGBT Driver Ground Pin. DRVIN CS VBAT IGBT Driver Input Pin. Input Current Setting Pin. Battery Supply Voltage Input Pin. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.
Exposed Pad (17) GND
Patent Pending www.richtek.com 4 DS9591-07 August 2007
+
STAT
Preliminary Absolute Maximum Ratings
(Note 1)
RT9591
Supply Voltage, VDD, VBAT, VDRV -------------------------------------------------------------------------------- -0.3V to 7V EXT -------------------------------------------------------------------------------------------------------------------- -0.3V to (VDD + 0.3V) DRVOUT -------------------------------------------------------------------------------------------------------------- -0.3V to (VDRV + 0.3V) IMCD ------------------------------------------------------------------------------------------------------------------ -0.5V to 7V Other I/O Pin Voltage ---------------------------------------------------------------------------------------------- -0.3V to 7V Power Dissipation, PD @ TA = 25C VQFN-16L 3x3 ------------------------------------------------------------------------------------------------------ 1.67W Package Thermal Resistance VQFN-16L 3x3, JA ------------------------------------------------------------------------------------------------- 60C/W Junction Temperature ---------------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260C Storage Temperature Range ------------------------------------------------------------------------------------- -65C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) --------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------------------- 200V
Electrical Characteristics
(VDD = 3.3V, VVDRV = 3.3V, TA = 25C, Unless Otherwise specification)
Parameter VDD Operating Voltage VDD UVLO Rising VDD UVLO Hysteresis VBAT Voltage Rising VBAT UVLO Hysteresis FB Voltage
Symbol VDD
Test Conditions
Min 1.8 -30
Typ -1.6 60 1.6 300 0.98 --1 0.01 0.01 10 3 3 16
Max 6.5 1.8 -1.81 -1 8 7 10 1 1 12 6 6 19
Units V V mV V mV V mV mV uA uA uA mA
VBAT(MIN)
-190
VFB 1.8V< VDD < 3V VFB 3V < VDD < 6.5V
0.96 -----8 VDD = 3.3V VDD = 3.3V VDD = 3.3V ----
Line Regulation
Switch-Off Current Switch-Off Current Shutdown Current IVDD+IVBAT EXT On Resistance to VDD EXT On Resistance to GND STAT On Resistance to GND
IVDD_SW_OFF VFB = 1.1V IVBAT_SW_OFF VFB = 1.1V IOFF Charge pin = 0V, VDD = 4.5V
Minimum Current on Secondary Side IIMCD
To be continued
Patent Pending DS9591-07 August 2007 www.richtek.com 5
RT9591
Parameter Charge Input High Threshold Charge Input Low Threshold Minimum Off Time IGBT Driver IGBT Driver Supply Voltage DRVIN Input High Threshold DRVIN Input Low Threshold DRVOUT On Resistance to VVDRV DRVOUT On Resistance to GND Propagation Delay (Rising) Propagation Delay (Falling) Voltage Detector Voltage Detector Trip (Falling) VDOUT On Resistance to GND VFBVD VVDRV Symbol
Preliminary
Test Conditions Min -0.4 VBAT = 1.8V to 6.5V VDD = 1.8V to 6.5V 280 Typ 0.7 0.7 360 Max 1.3 -430 Units V V ns
2.0 -0.4 VVDRV = 3.3V VVDRV = 3.3V VBAT = 1.8V to 6.5V VDD = 1.8V to 6.5V VVDRV = 2V to 6.5V(Note 3) FBVD Falling VDD = 3.3V -----
-1.0 1 6 6 ---
5.5 1.3 -8 8 20 200
V V V ns ns
0.96 --
0.99 16
1.02 19
V
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. VDRV is the IGBT gate driving power. Therefore, setting VDRV voltage must consider IGBT gate threshold voltage, and its driving capability.
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Preliminary Typical Operating Characteristics
10.0 9.0
RT9591
Charge Time vs. VBAT (47uF COUT)
4.5 4.0 3.5
Charge Time vs. VBAT (100uF COUT)
VOUT = 0V to 300V COUT = 100uF VDD = 3.3V
1
8.0 7.0
VOUT = 0V to 300V COUT = 47uF VDD = 3.3V
Charge Time (s)
Charge Time (s)
3.0 2.5 2.0 1.5 1.0 0.5 0.0
6.0 5.0 4.0 3.0 2.0 1.0 0.0 1.8 2.8 3.8 4.8 5.8 6.8
IPK-PRI = 1A
IPK-PRI = 1A
IPK-PRI = 1.5A
IPK-PRI = 1.5A
1.8
2.8
3.8
4.8
5.8
6.8
VBAT (V)
VBAT (V)
Efficiency vs. Output Voltage
90 85
Secondary Minimum Current vs. Temperature
11.0
VIN = 5V VIN = 2.5V
VIN = 3.3V
Secondary Minimum Current (mA)
IPK-PRI = 1.5A COUT = 100uF VDD = VBAT = VIN
10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 -50 -25 0 25 50 75 100 125
) Efficiency (%)
80 75 70 65 60 55 50 50 100 150 200 250 300
VIN = 1.8V
Output Voltage (V)
Temperature (C)
Output Voltage vs. Temperature
350 340
350 340
Output Voltage vs. Input Voltage
VDD = VIN VBAT = VIN TA = 25C VOUT set 300V
Output Voltage (V)
Output Voltage (V)
330 320 310 300 290 280 270 260 250 -50 -25 0 25 50 75 100 125
330 320 310 300 290 280 270 260 250 1.8 2.8 3.8 4.8
5.8
6.8
Temperature (C) ( )
Patent Pending DS9591-07 August 2007
Input Voltage (V)
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I PRI (1A/Div) VSW (10V/Div)
VOUT = 100V VOUT = 300V
RT9591
Output Voltage (100V/Div)
STAT (2V/Div)
I PRI (1A/Div) VSW (10V/Div)
Time (1us/Div)
Time (1us/Div)
STAT & Output Voltage
Preliminary
Patent Pending
VSW is the drain-to-source voltage of NMOS. I SEC (50mA/Div)
VOUT = 300V
VSW & Primary Current
VSW is the drain-to-source voltage of NMOS.
VSW & Primary Current
Time (1s/Div)
VSW (10V/Div) I SEC (50mA/Div) VSW (10V/Div)
VOUT = 100V
VSW & Secondary Current
VSW & Secondary Current
Time (1us/Div)
Time (1us/Div)
DS9591-07 August 2007
VSW is the drain-to-source voltage of NMOS.
VSW is the drain-to-source voltage of NMOS.
Preliminary Application Information
The RT9591 integrates a constant peak current controller for charging photoflash capacitor, an IGBT driver for igniting flash tube, and a voltage detector with open drain output to provide a cost effective photoflash solution. The photoflash capacitor charger uses constant primary peak current and constant secondary valley current control to efficiently charge the photoflash capacitor. Pulling the CHARGE pin high initiates the charging cycle. During ON time, the primary current ramps up linearly according to VBAT and primary inductance. A resistor connecting to CS pin determines the ON time of primary NMOS and consequently the primary peak current. During the OFF time, the energy stored in the flyback transformer is boosted to the output capacitor. The secondary current decreases linearly at a rate determined by the secondary inductance and the output voltage (neglecting the voltage drop of the diode). The secondary current is monitored by the IMCD pin. When the secondary current drops below 10mA, ON time starts again. The charging cycle repeats itself and charges the output voltage. The output voltage is sensed by a voltage divider connecting to the anode of the rectifying diode. When the output voltage reaches the desired voltage set by resistor divider, the HV detector will terminate the charging cycle, disable the charging block and pull high the STAT pin. The voltage sensing path is cut off when charging completed to minimize the output voltage decay. Both the CHARGE and STAT pins can be easily interfaced to a microprocessor in a digital system. Transformer The flyback transformer should be appropriately designed to ensure effective and efficient operation. 1. Turns Ratio The turns ratio of transformer (N) should be high enough so that the absolute maximum voltage rating for the NMOS drain to source voltage is not exceeded. Choose the minimum turns ratio according to the following formula: VOUT: Target Output Voltage
RT9591
VDS(MAX): Maximum drain to source voltage of NMOS 2. Primary Inductance Each switching cycle, energy transferred to the output capacitor is proportional to the primary inductance for a constant primary current. The higher the primary inductance is, the higher the charging efficiency will be. Besides, the RT9591 has a 360ns minimum-off time for correct current and voltage sensing. To ensure the charger operating in continuous conduction mode, the primary inductance should be high enough according to the following formula:
-9 LPRI 430 x 10 VOUT N x IPK - PRI
VOUT: Target Output Voltage N : Transformer turns ratio IPK-PRI : Primary peak current 430 x 10-9 : The maximum value of minimum-off time. 3. Leakage Inductance and Parasitic Capacitance The leakage inductance of the transformer results in the first spike voltage when NMOS turns off as shown in Figure 4. The spike voltage is proportional to the leakage inductance. The spike voltage must not exceed the dynamic rating of the NMOS drain to source voltage. Wellcoupling winding design decreases the leakage inductance. However, well-coupling winding design usually results in large parasitic capacitance between windings. The parasitic capacitance consequently causes initial current swing when NMOS turns on as shown in Figure 5. Trade off is necessary between leakage inductance and parasitic capacitance.
N(MIN)
VOUT VDS(MAX) - VBAT
Patent Pending
DS9591-07 August 2007
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RT9591
Spike voltage
Preliminary
Spike Voltage @Switching
The peak reverse voltage of the diode is approximately: VPK-R VOUT + (N x VBAT) The peak current of the diode equals primary peak current divide transformer turn ratio as the following equation: IPK-SEC = IPK-PRI/N Note: N is transformer turns ratio.
VSW (10V/Div)
I PRI (1A/Div)
NMOS The NMOS is the switching component of the flyback converter. Select adequate drain to source voltage and NMOS turn ON drain current is very important. For the RT9591 typical application circuit, If VOUT = 300V, VBAT = 6.5V, transformer turn ratio N = 15. VDS(MIN) = 300/15 + 6.5 = 26.5V. The NMOS minimum drain to source voltage should be greater than 26.5V.
Time (250ns/Div)
Figure 4
Swing Current @Switching
VSW (20V/Div)
Swing Current
In addition, make sure that VDD is higher than VGS(th) (Gate threshold voltage) so as to sufficiently turn on the MOSFET. Capacitor X5R ceramic capacitor 10uF/10V is recommended for input capacitor to well decouple the switching current. Figure 6 and Figure 7 compare the input current waveforms with different input capacitors.
I PRI (1A/Div)
Time (1us/Div)
Figure 5
Input Average Current & Output Voltage
4. Transformer Secondary Capacitance Any capacitance on the secondary can severely affect the efficiency. A small secondary capacitance is multiplied by N2 when reflected to the primary side. This capacitance forms a resonant circuit with the primary leakage inductance of the transformer. Therefore, both the primary leakage inductance and secondary side capacitance should be minimized. Rectifying Diode The rectifying diode should be with short reverse recovery time (small parasitic capacitance). Large parasitic capacitance increases switching loss and lowers charging efficiency. In addition, the peak reverse voltage and peak current of the diode should be sufficient.
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Input Average Current (500mA/Div)
VBAT = 3.3V CIN = 4.7uF
Output Voltage (100V/Div)
Time (1s/Div)
Figuer 6
Patent Pending DS9591-07 August 2007
Preliminary
Input Average Current & Output Voltage
Input Average Current (500mA/Div)
VBAT = 3.3V CIN = 10uF
RT9591
Adjustable Output Voltage The RT9591 senses output voltage by a voltage divider connecting to the anode of the rectifying diode during OFF time. This eliminates power loss at voltage-sensing circuit when charging completed. R3 to (R1+R2) ratio determines the output voltage as shown in the application circuit Figure1. The feedback reference voltage is 0.98V. If VOUT = 300V, in Figure 1 Photoflash Capacitor Charger Application according to the following equation:
VOUT = VFB x (1+ R1+ R2 R3 ), so R1+ R2 R3 = 305
Output Voltage (100V/Div)
Time (1s/Div)
Figure 7 Adjustable Input Current The RT9591 simply adjusts peak primary current by a resistor RCS connecting to CS pin as shown in Function Block Diagram. RCS paralleled with internal 1M resistor determines the ON time of primary NMOS. During the ON time, the primary current ramps linearly with a slope = VBAT/LPRI. Consequently, the current setting resister (RCS) could be calculated as: Ra = (IPK - PRI - 8 x 10 -3 x N) x LPRI 30 x 10 -12 1M x Ra () 1M - Ra
R3 is recommend 1K; R1 and R2 are used 150K for reducing parasitic capacitance coupling effect of FB pin. R1 and R2 MUST be greater than 0805 size resister for enduring secondary HV. Lower Charging Current at Low Battery Voltage The RT9591 integrates a voltage detector with open drain output. This voltage detector is specially designed for lowering peak primary current and minimizing the impact to battery voltage at low VBAT condition as shown in Figure 8. The voltage detector senses VBAT through a resister divider R6 and R7 and compares it with internal 1V reference voltage. When the sensed voltage is lower than the reference voltage, VDOUT pin goes low and changes the resistance connecting to CS pin and the ON time. For example, if R6 equal 1.5M and R7equal 1M, VDOUT pin change status form open to ground when VBAT voltage under 2.5V. And current setting resister R4 and R5 can set different resistance for different input current when VBAT voltage under detector voltage. Figure 9 shows the lower charging current waveform. When VBAT voltage under 2.5V, the input average current become approximately 600mA to 460mA.
RCS =
Where IPK-PRI is the primary peak current and N is the turns ratio of transformer. Users could select appropriate RCS according to the battery capability and required charging time. Minimum IPK-PRI Limitation
The IPK - PRI setting must
430 x 10 -9 x VOUT , N x LPRI
where 430 x 10-9 is the maximum value of minimum off time. If lower IPK-PRI setting limitation is required, you may change transformer to incease N x LPRI product.
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RT9591
V BAT
Preliminary
T1 1 : 15 V OUT
+
C IN 10uF
R6 1.5M
Q1
R1 150k
100uF/3 00V
C OUT
FBVD VDD
V DD 10uF R8 100k
VBAT
RT9591
VDOUT STAT CHARGE PGND
DRVOUT GNDDRV GND CS FB
IMCD
EXT
R7 1M
R2 150k
DRVIN VDRV
R4 1M R5 2M
R3 1k
Figure 8. Lower Charging Current Application Circuit
Lower Charging Current
(1V/Div) Under 2.5V
t t
(200mA/Div)
VBAT Input Average Current Output Voltage
V DRVIN
Change input current
V t
2.5
V s
(100V/Div)
Figure 10. IGBT Driver Input Signal
Time (1s/Div)
Figure 9 IGBT Driver Input Signal The slew rate of IGBT driver input DRVIN should be higher than 2.5V/s for normally triggering the IGBT as shown in Figure 10. Layout Guide 1.Both of primary and the secondary power paths should be as short as possible. 2.Keep FB node area small and far away from nodes with voltage switching to reduce parasitic capacitance coupling effect. 3.The NMOS ground and feedback ground should be connect to VBAT ground for reduce switching noise.
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Preliminary Outline Dimension
SEE DETAIL A L
1
RT9591
D
D2
E
E2
1
1 2
e A A1 A3
b
2
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3 b D D2 E E2 e L
Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 2.950 1.300 2.950 1.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 3.050 1.750 3.050 1.750
Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.116 0.051 0.116 0.051 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.120 0.069 0.120 0.069
V-Type 16L QFN 3x3 Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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